1. Field of the Invention
This invention relates to information memory device for information processing systems or the like, and more particularly to a memory device which enables the use of partially defective memory elements that normally would be rejected as unusable during the production process.
2. Description of the Prior Art
Generally, the memory device of this kind is always composed of an assembly of perfect memory cells so that its normal operation appears to the user to be performed even if any of the memory cells is selected. In recent years, the memory device of this type is formed with semiconductor memory elements, each having a large number of memory cells integrated on a silicon chip. However, the yield of good semiconductor memory elements such that all the memory cells on the silicon chip are perfect is low. Further, even if only one memory cell becomes defective in the operation of the memory device, the whole memory element having the defective cell is rendered unusable. Therefore, the memory device of this type in the prior art is very uneconomical.
In the prior art, one method that has been employed for a memory device having a very small number of defective memory cells is, for example, to previously write information with the use of an error correcting code in the memory and to automatically correct the information read out therefrom. However, this method is limited only to the case where a very small number of bits of a word are stored in the defective cells. And even if this method is applied to a memory device employing a large number of partially defective memory elements, no error correction can be achieved correctly, so that the above method is ineffective. Further, in order to use the memory elements having defective memory cells, it is also possible to wire the memory elements so that the wiring by-passes the defective memory cells. However, this method requires re-processing of the memory elements, and hence has the disadvantage of inevitably increasing the manufacturing cost of the semiconductor memory element having a large number of memory cells integrated.